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Product Specification
AHA4013B
12.5 MBytes/sec Reed-Solomon Error Correction Device
2365 NE Hopkins Court Pullman, WA 99163-5601 tel: 509.334.1000 fax: 509.334.9000 e-mail: sales@aha.com www.aha.com
advancedhardwarearchitectures
PS4013B-0600
Advanced Hardware Architectures, Inc.
Table of Contents
1.0 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Conventions, Notations and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 Definition of Correction Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 Correcting Capability and Polynomials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5.1 Shortened Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 Reset and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.1 Initialization Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 Encode, Decode or Pass-Through Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.8 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 Data Rates and Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9.1 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9.2 Continuous Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 Reed-Solomon (ECC) Module and Error Rate Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 Determining Decoder Performance Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.12 Erasures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 Signal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 Output Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 Power & Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.0 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.0 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 Available Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Part Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.0 Related Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Appendix B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Typical Applications Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Data Input and Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Burst and Continuous Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes . . . . . . . . . . . . . . . . . 11 CLK Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Initialization and Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Input - Buffer Always Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Input - Buffer Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CRTN Timing - Reverse Order Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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Tables
Table 1: Table 2: Table 3: Table 4: Initialization Register Settings for Encode, Decode and Pass-Through Operations . . . . . . . . . . . . . . . . . . 7 Burst Operation Using 50 MHz Clock and 1 Clock/Byte, Forward Order Output . . . . . . . . . . . . . . . . . . . . . 9 Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward Output Order. . . . . . . . 10 Continuous Operation for IESS-308 Codes Using 50 MHz Clock and Specified Clocks/Byte, Forward Output Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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1.0
INTRODUCTION
The AHA4013B is a single chip integrated circuit that implements a high speed Reed-Solomon Forward Error Correction algorithm. The AHA4013B is a member of the AHA PerFEC family of high speed forward error correction (FEC) devices conforming to the Intelsat IESS-308 specification. The device supports several programmable parameters, including, block size, error threshold, number of check bytes, order of output and mode of operations. Shortened blocks are supported without requirement of zero padding typically required in Reed-Solomon decoders. The data input port is used to initialize the programmable parameters and the two on-chip buffers are used to input and output data. Discontinuities in data flow may be controlled by dedicated control pins. High operating frequency, input and output data rate flexibility, low processing latency and various programmable parameters make this device ideal for many applications including: DTV, DBS, ADSL, Satellite Communications, ISDN, High Performance Modems and networks. This specification provides full electrical and mechanical information to help a system engineer develop a system using AHA4013B. This document contains descriptions on correction terms, pinout, functions and features, DC and AC characteristics, package and mechanical specifications, ordering information and Related Technical Publications. Software simulation of the RS code as implemented in the device is also available. Please contact AHA or its authorized sales representatives worldwide or visit our web site at http://www.aha.com for copies of Related Technical Publications and software simulation.
FLEXIBILITY * Programmable to correct from 1 to 10 error bytes or 20 erasure bytes per block * Block lengths programmable from 3 to 255 bytes * Encode, decode or pass-through capability inline with data flow * Outputs corrected data or correction vectors in forward or reverse order * Continuous or burst data transfer * Programmable error threshold to help determine channel performance SYSTEM INTERFACE * Byte wide synchronous I/O ports with internal buffering on both ports * Dedicated control pins permit discontinuities in system data flow OTHERS * 44 pin PLCC; 50 mil lead pitch * Pin compatible with lower performance AHA4011/12 * Plug compatible with AHA4011/12 except for an initialization register setting * Software emulation of the algorithm available
1.2
CONVENTIONS, NOTATIONS AND DEFINITIONS
1.1
FEATURES
HIGH PERFORMANCE * Polynomial complies to Intelsat IESS-308; RTCA DO-217 Appendix F, Revision D and proposed ITU-TS SG-18 (Formerly CCITT SG18) standards * 50 MBytes/sec burst transfer rate with a 50 MHz clock for all block lengths * Sustained data transfer rate of 12.5 MBytes/sec for block lengths from 54 bytes through 255 bytes using a 50 MHz clock * Processing latency time less than 12.2 sec in continuous operation for block lengths of 100 bytes
- Certain signals are logically true at a voltage defined as "low" in the data sheet. All such signals have an "N" appended to the end of the signal name. For example, RSTN and DSON. - "Signal assertion" means the output signal is logically true. - Hex values are defined with a prefix of "0x", such as "0x10". - A range of signal names is denoted by a set of colons between the numbers. Most significant bit is always shown first, followed by least significant bit. For example, DI[7:0] represents Data Input Bus 7 through 0. - A product of two variables is expressed with an "x", for example, N x Ci represents Codeword Length multiplied by Input clocks/byte. - Mega Bytes per second is referred to as MBytes/ sec or MB/sec.
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Advanced Hardware Architectures, Inc. 1.2.1 TERM
K
DEFINITION OF CORRECTION TERMS NAME (other references)
Message Length (user data or message bytes)
DEFINITION
Number of user data symbols in one message block. Size of a symbol in AHA4013B is 8-bits. Message length is K = N - R. The first message byte is referred to as XK-1; the last message byte is X0. Symbols appended to the user data to detect and correct errors. The number of check symbols required in a system is R E + 2e.* The first check symbol is referred to as YR-1; the last check symbol is Y0. Sum of message and check symbols. N = K + R. Maximum number of error corrections performed by the device. The value is t = Integer N - K . ------------2The threshold limit to determine uncorrectability of a Codeword and the number of check bytes allocated for correction-only purposes (not for detection). An error is defined as an erroneous byte whose correct value and position within the message block are both unknown. An erasure is defined as an error whose position is known within the message block.** A measure of the burden of correction being placed on the capabilities of the device for that message block. The value G = 2e + E.
RANGE (number of bytes)
1 through 253 (1, 2, 3, 4... 253) 2 through 20 in increments of 1 (2, 3, 4... 20) 3 through 255 (3, 4, 5, 6... 255) 1 through 10 (1, 2, 3... 10) 2 through 20 (2, 3, 4... 20) 0 through N 0 through N 0 through R
R
Check Symbols (parity or redundancy) Codeword Length (block length) Error Corrections
N t
P
Error Threshold
e E G
Number of Errors Number of Erasures Burden of Correction
* For every 2 check bytes, the AHA4013B can correct either 2 erasures or 1 error. ** An erasure is detected by a parity detector or a signal dropout detector. The presence of an erasure is indicated by asserting the ERASE signal when the erased byte is clocked into the AHA4013B.
2.0
FUNCTIONAL DESCRIPTION
This section describes an architectural overview of the chip and its many functions, features and operations. The block diagram for the chip shows the Reed-Solomon ECC module, the Input and Output Buffers, and their associated control. All input and output data are clocked on the rising edge of CLK.
2.1
FUNCTIONAL OVERVIEW
The AHA4013B Reed-Solomon codec (coder/ decoder) is a member of the AHA PerFECTM family of high speed forward error correction (FEC) devices. This single chip, three-layer metal, CMOS device can operate in encode, decode or pass-through modes. The ECC core implements a full error correcting Reed-Solomon decoder. This code is capable of correcting up to 10 (t=10) byte-errors or 20 (t=10) erasures in a RS block.
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The ECC core has three phases of operation: Data In, Calculation and Data Out. Data to be processed is first input into a single ported Input Buffer using a control signal DSIN. ECC core arbitrates for the input data out of the Input Buffer. ECC core has access to the Input Buffer on clock edges where DSIN is not asserted. Each block is processed within the ECC core and calculations are made. The entire block is processed through the ECC core, and transferred into the Output Buffer. The device asserts RDYON signal and holds active until the Output Buffer is completely emptied. The ECC core loads the Output Buffer in reverse order for either operation. Data may be strobed out of the device in forward or reverse order. If forward order is desired, output data cannot be strobed out of the device until the entire block has been loaded into the Output Buffer.
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The use of internal buffers is restricted per the rules defined in Section 2.9 Data Rates and Latencies. Maximum delay required for each block of a given length to pass through the device is fixed, and does not vary with the location or the number of errors received. This delay (or latency), expressed in the number of clocks is discussed in a later section. Correcting "erasures" takes only half as much of the correction capability of the RS code as it takes to correct "errors", since the position information is already known for "erasures". The correction ability of the code is bounded as: R # erasures + 2(# errors) Valid block length (N) is defined by the relationship: R + 1 N 255 where R ranges from 2 to 20. A complete codeword can therefore range from a minimum of 3 bytes to a maximum of 255 bytes. For further discussion on error rate performance, refer to Section 2.10 Reed-Solomon (ECC) Module and Error Rate Performance.
2.2
CORRECTING CAPABILITY AND POLYNOMIALS
Compared with other codes, RS codes require relatively few "overhead" check bytes to be added to the data stream to achieve a high degree of error detection and correction. Since the AHA4013B deals with bytes (or symbols) rather than with individual bits, when a byte is in error it does not matter how many bits within the byte are corrupted; it is counted as one error. The Reed-Solomon code is defined over the finite field GF(28). The field defining primitive polynomial is: P(x) = x8 + x7 + x2 + x + 1 and the generator polynomial, dependent on the variable R, is given by:
G(x) =
119 + R i = 120
Figure 1:
Block Diagram
RDYIN ERASE DI[7:0] CLK
RDYIN
DI
CLK
REGISTER
INPUT BUFFER
367x9
( x - i )
RSTN
RSTN GND GND
where R {2, 3, 4, 5,... 20} for the AHA4013B. This polynomial is specified in international standards, Intelsat IESS 308; RTCA DO-217 Appendix F (Rev D) and the proposed CCITT SG-18. For every 2 check bytes, the decoder corrects either 2 erasures or 1 error. An erasure can be determined with a parity detector or a signal dropout detector external to the chip. An erasure is indicated by the ERASE signal when the erased byte is clocked in the device.
DSIN
DSIN
CONTROL
ECC CORE
VDD VDD
DSON
DSON
OUTPUT BUFFER
256x9
REGISTER
RDYON
CRTN
DO
RDYON
CRTN
DO[7:0] ERR
Figure 2:
Typical Applications Diagram
ENCODER COMMUNICATIONS
8
DECODER
8
DATA SOURCE A
8
AHA4013B ECC COPROCESSOR
B
CHANNEL 1 TO x BITS WIDE
AHA4013B ECC COPROCESSOR
8
DATA SINK
C
BLOCK FORMAT AT: SYSTEM CONTROLLER
A KDATA PLUS R "DUMMY" BYTES B KDATA PLUS R CHECK BYTES C KDATA BYTES
SYSTEM CONTROLLER
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2.3
SIGNAL DESCRIPTIONS
Output Pins
RDYIN Ready Input. Indicates the chip's ability to accept data input on DI. If active, DSIN is allowed to enable the loading of input data on DI. When inactive, DSIN is ignored. Signal is active low. DO[7:0] Data Output. The output byte is available on this bus. The value of the output byte is undefined if RDYON is inactive. Requires an acknowledge strobe, DSON, at a rising edge of the clock to increment internal address counter and output the next location in the buffer. DO bus is always driven and is not tristated by the device. RDYON Ready Output. This output pin indicates the chip's ability to generate output data. If active, DSON is allowed to increment the internal address counter for the next data byte. When inactive DSON is ignored and DO is undefined. Signal is active low. CRTN Correctable. The output pin when active indicates the block did not exceed the error threshold programmed by P. Error threshold must be programmed with the same value as the number of check symbols R if erasures are not used. This signal is valid when the first message byte, XK-1, of the block is available out of the chip. During all other times the signal is undefined. Signal is valid for at least one clock. Active low. ERR Error. Output pin indicates the current value on DO[7:0] is a corrected byte. Active high.
Input Pins
DI[7:0] Data Input Bus. The input byte and ERASE are latched on the rising edge of the clock when both DSIN and RDYIN are active. If either DSIN or RDYIN are inactive, the DI and ERASE are ignored. DSIN Data Input Strobe. Enables data from DI to be loaded into the chip. When RDYIN is active, DSIN being active on the rising edge of the clock loads the input data in the device. DSIN must be active for one clock edge only per each input byte. DSIN is ignored if RDYIN is inactive. Signal is active low. DSON Data Output Strobe. This input strobe acknowledges to the chip that data available on the Output Bus, DO, has been received by the system. The device uses this strobe to increment its internal address counter to the next data location. DSON must be active for one clock edge only per each output byte. DSON is ignored if RDYON is inactive. Active low. ERASE Erasure input flag for symbol currently on DI. Signal is active high. ERASE signal is used for marking all check Bytes as erasures (dummy check Bytes) during encode operation. It is also used to mark input symbols that contain errors during decoding. If not used, connect this signal to ground. RSTN Reset. Input pin. When RSTN is active and DSIN and DSON are inactive, the device forces all internal control circuitry into a known state and initializes all data path elements. RSTN is active during Initialization Phase. In this phase, internal registers are programmed by using DI and DSIN. Signal is active low. CLK Clock. System clock input. Refer to Section 4.4 AC Electrical Characteristics for clock requirements.
2.4
PINOUT
INPUT DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DISN CLK GND 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDD GND VDD GND GND VDD *NC *NC VDD GND GND
7 8 9 10 11 12 13 14 15 16 17
AHA4013B-050 PJC
VDD VDD GND VDD RSTN ERASE DSON RDYIN RDYON GND GND
*NC = No connect, reserved for future considerations.
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DO0 DO1 DO2 DO3 DO4 DO5 DO6 VDD DO7 ERR CRTN OUTPUT
18 19 20 21 22 23 24 25 26 27 28
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2.5
DATA FLOW
The device is first initialized for various programmable parameters including: Erasure Multiplier, Error Threshold, Number of Check bytes, Number of Message bytes per block, Block Length and a Control byte. Following this six-byte initialization, the device may be used to encode, decode or pass-through multiple blocks of data. The device requires reinitialization when the parameters are changed or a reset is required. The device processes data as "blocks" containing Message and Check Bytes. Order of input bytes must be first message byte XK-1 through last message byte X0, followed by first check byte YR-1 through last check byte Y0. The device processes the block in this manner: - a block is clocked into the Input Buffer; - transferred into the ECC module; - passed to the Output Buffer in the reverse order from what was received at the Input Port; and
- clocked out through the Output Port via the Output Buffer. Consecutive blocks may be input into the Input Buffer while the Output Buffer is being emptied. Data is available through the Output Port in forward or reverse order. Forward order clocks out the block the same as input and reverse order clocks the check byte Y0 through check bytes YR-1 followed by message byte X0 through message byte XK-1.
2.5.1
SHORTENED BLOCKS
This device allows for shortened RS blocks, thus not requiring zero padding when decoding. During encoding, conversely, zero padding is not performed. When the device is programmed to decode a block of less than 255 Bytes, only the message bytes followed by check bytes are sent. Prepending with zero value bytes to fill out the block to 255 Bytes is not required.
Figure 3:
Data Input and Output Order
Y0 Y1 . . . YR-2 YR-1 X 0 X 1 . . . X K-2 X K-1
Last Byte In First Byte In
INPUT BUFFER
ECC Core
OUTPUT BUFFER
Data Available Reverse Order X K-1 . . . X0 YR-1 . . . Y0 Data Available Forward Order Y0 . . . YR-1 X0 . . . X K-1
Last Byte Out
First Byte Out
2.6
RESET AND INITIALIZATION SEQUENCE
Reset and initialization first requires pulling the RSTN low signal for at least two clocks while the DSIN and DSON signals are held inactive, i.e., high Following this sequence, the six internal registers, referred to as "Initialization Registers" are strobed by DSIN. These bytes are loaded in order of 1 through 6. The RSTN must be active low for at least two clocks before the first initialization byte is strobed in and remain active for at least one clock after the final byte. RSTN must be high for at least two clocks before the first message byte can be strobed into the device. For a detailed timing diagram, see Figure 7: Initialization and Reset Timing.
The chip must be reset and initialized any time a reset is necessary. Caveat: All six registers must be initialized correctly for proper operation of the chip. The device has no provisions for reading back Initialization Register settings. This sequence must be used if the device needs to be reset or any one register needs updating, i.e., all registers must be reinitialized for a change to any one register.
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Advanced Hardware Architectures, Inc. 2.6.1 INITIALIZATION REGISTERS
[3] Forward Order Control Outputs the block in reverse order 1 Outputs the block in forward order RAW Raw Data 0 Outputs corrections or corrected data per the CRCTS bit 1 Outputs uncorrected, raw input data or 0's depending upon the CRCTS bit setting (See table below). NOPAR bit and CHECK BYTE register settings are ignored. ERC Erasure Rejection Control. This bit is only used by the device when the Erasures exceed the ERROR THRESHOLD or R settings. This bit is ignored when the Erasures are less than or equal to ERROR THRESHOLD or R. 0 If Erasures are greater than the ERROR THRESHOLD or R then erasures are discarded and full correction is performed. The block is flagged uncorrectable and the output CRTN will be high during the last output byte of the block. 1 If Erasures are greater than ERROR THRESHOLD or R then erasures are discarded and full correction is performed. The output CRTN will be high only when the block is uncorrectable. Reserved, Set to 0. FOR 0
BYTE 1, ERASURE MULTIPLIER: [7:0] Multiplier value that must be programmed as shown in Appendix A. The table shows a value to be programmed corresponding to the block length selected. BYTE 2, ERROR THRESHOLD: [4:0] The threshold for determining uncorrectability of a data block, and the number of check bytes allocated for correction only purposes. When not using erasures, set to the same value as BYTE 3, CHECK BYTES. Minimum value of 0x02 sets the Threshold to 2 and 0x14 sets to the maximum, 20. [6:5] Reserved. Set to 0. [7] Reserved. Must be set to 1. BYTE 3, CHECK BYTES: [4:0] Number of check bytes in RS code, R. Minimum setting of 0x02 indicates two check bytes for R = 2 and 0x14 indicates the maximum of 20. [6:5] Reserved. Set to 0. [7] Reserved. Must be set to 1. BYTE 4, MESSAGE BYTES: [7:0] Number of message bytes in code, K. Minimum setting of 0x01 indicates 1 byte, setting to 0xFD indicates the maximum 253 message bytes. BYTE 5, BLOCK LENGTH: [7:0] Number of bytes in block, N. Setting to 0x03 indicates 3 bytes, setting to 0xFF indicates 255 bytes. BYTE 6, CONTROL BYTE: [0] RESERVED Reserved. Set to 0. [1] NOPAR Parity Symbol Control 0 Check bytes are output following the message bytes. 1 Check bytes are not output following the message bytes. Correction will be done regardless depending upon the bit 4, RAW, setting. [2] CRCTS Correction Control 0 Outputs correction vectors; to obtain corrected data, externally XOR the correction vector with the corresponding message or check byte. 1 Outputs corrected data
[4]
[5]
[7:6]
RAW CRCTS Output 0 0 Correction vectors 0 1 Corrected data 1 0 Zero 1 1 Uncorrected raw input data
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PS4013B-0600
Advanced Hardware Architectures, Inc.
2.7
ENCODE, DECODE OR PASS-THROUGH OPERATIONS
it is received. In all three operations, the input block flows through the Input Buffer into the ECC module and out of the Output Buffer. Latencies for all three operations are the same. The device is initialized for the three operations as shown in the table below.
The device performs three functions: encoding, decoding and pass-through. As an encoder the device outputs the message block followed by "corrected" check bytes. As a decoder, the device outputs the corrected message bytes or correction vectors with or without check bytes following the message. In passthrough operation, the device passes the input data as
Table 1:
Initialization Register Settings for Encode, Decode and Pass-Through Operations BIT(S)
[7:0] [7:0] [7:0]
INITIALIZATION REGISTER
ERASURE MULTIPLIER ERROR THRESHOLD CHECK BYTES MESSAGE BYTES BLOCK LENGTH
ENCODE
DECODE
PASS-THROUGH
CONTROL BYTE
Appendix A value Set to R Set to R Set to the Number [7:0] of Message Bytes in block, K Set to the total of [7:0] Message and Check bytes, N 0 (RESV) 0 1 (NOPAR) 0 2 (CRCTS) 1 3 (FOR) System specific 4 (RAW) 0 5 (ERC) 0 [7:6] Reserved 0
Appendix A value Appendix A value R or less R R R K N 0 System specific System specific System specific 0 System specific 0 K N 0 0 1 System specific 1 0 0
As an encoder, the device is used with the Erasures feature enabled in the following sequence. (Asserting the ERASE signal high enables the Erasure feature.) 1) After initialization, the device receives the message data followed by "dummy" check bytes. "Dummy" check bytes are clocked into the device with the ERASE signal asserted. The number of "dummy" check bytes must equal R. 2) The ECC core processes the block by "correcting" the check bytes and feeding the codeword into the Output Buffer in reverse order. 3) The block is then made available on the output bus, DO. The state of the output RDYON determines the availability of data. ERR signal is asserted while the "corrected check bytes" are output on the output bus, DO. CRTN is asserted low during the last byte out of the chip indicating that the previous block did not exceed the error threshold.
As a decoder, the device works similar to the encode operation in the following sequence. 1) Following initialization, the system clocks the message data and the check bytes into the Input Buffer. ERASE signal may be asserted as desired by the system. State of the output signal, RDYIN determines the chip's ability to accept data input on the DI bus. 2) The ECC Core processes the block by performing necessary corrections, and feeds the codeword into the Output Buffer in reverse order. 3) The data is available on the output port. The state of the output signal, RDYON determines the availability of valid data. An output byte which has been corrected is indicated by the device asserting ERR. CRTN may be high or low depending upon the THRESHOLD Register and ERC bit programmed and the errors encountered.
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In pass-through operation, data flows through the device similar to the encode and decode operations. During initialization the device is programmed as shown above. Check Bytes are programmed in the range of 0x02 to 0x14. The Block length here is the sum of Message Bytes and Check Bytes like encode and decode modes of operation even though the device passes through the block of data unchanged. 1) Following initialization, the system clocks the codeword into the Input Buffer. 2) The codeword is processed by the ECC module and passed on to the Output Buffer without correction. 3) The uncorrected codeword is available at the output port. State of the RDYON determines the availability of valid data. The ERASE input is ignored during the Input phase and ERR and CRTN outputs are not valid. Caveat: The device has no provisions for indicating the start and/or end of message or check bytes. It is the system designers responsibility to keep track of message and check bytes transitions, if required. processing latency period. Data is input into the Input Buffer and processed through the ECC core. After a processing latency period the entire block of data is transferred to the Output Buffer. While the Output Buffer is being emptied, the Input Buffer is simultaneously filled with the following block at the maximum rate. Input and output rates are controlled by the clock speed and clocks/byte. Continuous operation requires a minimum of 4 clocks/byte depending upon the block size. Maximum data transfer rates for continuous rate vary accordingly. Blocks may be processed continuously through the device. If the chip is operated with continuous data streams, the RDYIN and RDYON pins will always be active (after the initial latency). Therefore, they need not be used. Caveat: System designer should be aware that data is put into the Output Buffer in reverse order. Therefore, RDYON may become inactive between blocks in forward order if data is output faster than Output Buffer is filled.
2.9
DATA RATES AND LATENCIES
2.8
BUFFERS
The Input Port contains a single-ported 367x9 buffer. The Output Port contains a single-ported 256x9 buffer. These buffers store input and output data during the correction process and help maintain the desired system data rate. A Reset operation as described in the Initialization Sequence section clears the buffers. The use of internal buffers is restricted per the rules defined in Section 2.9 Data Rates and Latencies. These rules define the limitations of using the buffers to temporarily store more than one block. It is highly recommended that the system designer clearly understand these rules prior to designing the system. The Input Buffer receives input data on the DI bus when the ECC module is in the calculation or in dataout phases at the desired system rate. The ability of the Input Buffer to accept data is indicated by RDYIN. The Output Buffer accepts corrected data from the ECC during the data-out phase. RDYON is asserted low when the Output Buffer is able to output data. Data flow through the device may occur in burst or continuous rates. The number of clocks per byte used to input or output determines burst or continuous operating conditions. Figure 4 shows the two operations. Burst operation permits data to be clocked in and out of the device at the maximum rate, i.e., 1 clock per byte. In burst operation, consecutive data blocks are clocked into the device following a
Page 8 of 24
This section describes data rates and processing latencies for burst and continuous operations. Processing latencies are the same in encode, decode or pass-through operations. The number of clocks used to clock in and out of the device determines the operation. The input and output rates need not be the same. No registers are required to program the device for either operation. Continuous block flow is achieved by using the appropriate number of clocks per byte and block length. Alternatively, data flow into and out of the device is controlled using control signals, DSIN and DSON.
2.9.1
BURST OPERATION
Maximum processing latency, in forward order, expressed in number of clocks, for burst operation is determined by: N x Ci + R + 60 + N Definitions: Ci = input clock rate per byte. If Ci = 1, use a value for Ci of 2 in the latency equation N = block length R = number of check bytes Processing Latency = Delay from first input byte to first output byte In reverse order, processing latency is approximately N clocks less than above. For a 50 MHz system using 1 clock per byte, latencies and data rates for forward order output are shown in the table for burst operation. Input and Output Burst Rates in all cases will be 50 MBytes/
PS4013B-0600
Advanced Hardware Architectures, Inc.
sec. Note: Other frequency operations may be derived similarly. Output Buffer may be used to hold data from one block while the Input Buffer is being filled with the following block. Two rules listed in the caveats are required to accomplish this. These are illustrated in Figure 4. Caveats: 1. Output of block i must start coincident with or before the input of block i + 1. 2. Output of block i must be complete: Processing Latency - N - 8 clocks after the start of block i + l on the input.
Table 2:
Burst Operation Using 50 MHz Clock and 1 Clock/Byte, Forward Order Output CHECK BYTES `R' = 2 MAXIMUM MAXIMUM AVERAGE LATENCY LATENCY RATE
(# of clocks) 137 212 362 512 662 827 (secs) 2.74 4.24 7.24 10.24 13.28 16.56 (MBytes/sec) 9.13 11.79 13.75 14.63 15.13 15.38
CHECK BYTES `R' = 20 MAXIMUM MAXIMUM AVERAGE BLOCK LATENCY RATE LENGTHS `N' LATENCY
25 50 100 150 200 255
(# of clocks) 155 230 380 530 680 845 (secs) 3.10 4.60 7.60 10.64 13.60 16.88
(MBytes/sec) 8.06 10.88 13.13 14.13 14.75 15.13
N Average Rate = --------------------------------------------------------------Maximum Latency ( sec )
2.9.2
CONTINUOUS OPERATION
Equation 2:
N x Ci N x C m ( N - 1 ) x C i R + 48 + --------------- + ----------------Ci - 1 Cm - 1
Multiple blocks of data may be processed through the device continuously as shown in Figure 4. Consecutive blocks are input into the device at the rate of Ci clocks/byte. The output data stream may or may not be continuous depending on whether parity is being output (controlled by NOPAR) and the choice of Co. Continuous operation is described by several equations. The following terms are used in these equations: Ci - Input clock rate per byte: Ci 4 for continuous operation Co - Output clock rate per byte: Co 2 Cm - Minimum of Ci and Co: If Ci < Co then Cm = Ci else Cm = Co N - Reed-Solomon block length K - Reed-Solomon message length R - Reed-Solomon parity length (R = N - K) L - Output data length: If parity is being output from the chip (NOPAR = 0), L = N; else if the parity is not being output (NOPAR = 1) L=K
B. Processing Latency
Processing latency is the time from the beginning of a block on the input to the block being ready for output. Maximum processing latency, expressed in number of clocks, for continuous operation is: Equation 3:
N x Cm Latency = ( N - 1 ) x C i + 60 + R + ----------------Cm - 1
C. Start and End of Output
Similar to the burst operation, Output Buffer may be used to temporarily "hold" data from one block while the Input Buffer is being filled. However, these conditions must be satisfied: the output of a data block must start after the latency equation (Equation 3) is satisfied, but before the maximum delay is reached. The maximum delay is: Equation 4:
N x Ci maximum_delay = 3 x N x C i - L x Co - --------------Ci - 1 if maximum_delay -------------------------------------------- 367, then maximum_delay = 367 x C i Ci if maximum_delay -------------------------------------------- > 2 x N, then maximum_delay = 2 x N x Ci Ci
A. Conditions for Continuous Operation
The allowable input and output data rates are related to the Reed-Solomon block length by the following two inequalities. Ci, Co, N and K must be chosen so that these equations are satisfied. Equation 1:
N x Cm R + 60 + ----------------Cm - 1 --------------------------------------- + N 367 Ci
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Advanced Hardware Architectures, Inc.
Data of one block must be fully emptied L x Co clocks after the start of empty process. All of the conditions on the maximum delay given in Equation 4 must be satisfied. If any are not, the output data stream will begin to inhibit ECC processing. Eventually this will cause the input buffer to over fill and RDYIN to become inactive.
Figure 4:
Burst and Continuous Operations
(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order. Block i is the first input block, block i + 1 is second input block. XK - 1 is the first input message byte of a block. Yo is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst Operation - Caveats.)
Burst Operation
Input Data:
Block i+1 Y 0 . . . . . . . . . . X K-1 Block i+1 Y 0 . . . . . . . . . . X K-1
2
Block i
1
Y 0 . . . . . . . . . . X K-1
Output Data:
Block i Y 0 . . . . . . . . . . . . . . . . . . X K-1 Processing Latency
Continuous Operation
Input Data: Output Data:
Block i+3 Block i+3 Block i+2 Block i+1 Block i Y0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Block i+2 Block i+1 Block i
Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1 Y 0 . . . . . . . . . . X K-1 Y0 . . . . . . . . . . X K-1
For a 50 MHz system using the required clocks per byte, maximum latencies and data rates for forward order output are shown in the table for continuous operation. Input and Output rates are assumed the same in this table. Note: Other frequency operations are also possible.
Table 3:
Continuous Operation Using 50 MHz Clock and Specified Clocks/Byte, Forward Output Order CHECK BYTES `R' = 2 MINIMUM MAXIMUM MAXIMUM REQUIRED DATA RATE LATENCY
(clocks/byte) 5 5 4 4 4 4 4 (MBytes/sec) 10.0 10.0 12.5 12.5 12.5 12.5 12.5 (secs) 4.26 7.39 11.82 17.16 22.50 25.16 28.36
CHECK BYTES `R' = 20 MINIMUM MAXIMUM MAXIMUM BLOCK REQUIRED DATA RATE LATENCY LENGTHS `N'
25 50 100 150 200 225 255
(clocks/byte) (MBytes/sec) 6 8.34 5 10.00 4 12.50 4 12.50 4 12.50 4 12.50 4 12.50 (secs) 5.08 7.75 12.18 17.52 22.86 25.52 28.72
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 50 MHz clock.
Note: Other frequency operations are also possible.
Page 10 of 24
PS4013B-0600
Advanced Hardware Architectures, Inc. Table 4: Continuous Operation for IESS-308 Codes Using 50 MHz Clock and Specified Clocks/Byte, Forward Output Order MAXIMUM DATA RATE
(MBytes/sec) 12.5 12.5 12.5 12.5 12.5
MINIMUM BLOCK MESSAGE ERROR REQUIRED LENGTHS `N' LENGTH `K' CAPABILITY `t'
126 194 208 219 225 112 178 192 201 205 7 8 8 9 10
MAXIMUM LATENCY
(# of clocks) 742 1107 1181 1242 1276
MAXIMUM LATENCY
(secs) 14.84 22.14 23.62 24.82 25.52
(clocks/byte) 4 4 4 4 4
Appendix B shows a spreadsheet table of block lengths vs. latencies for a 50 MHz clock system.
2.10 REED-SOLOMON (ECC) MODULE AND ERROR RATE PERFORMANCE
The module implements a full error correcting Reed-Solomon (RS) decoder whose function is to perform the necessary corrections on the input blocks. The code used by the decoder is capable of generating corrections for up to 10 (t = 10) byteerrors in an RS block over the block length between R + 1 to 255 bytes. The number of message bytes in an RS block, K, is equal to the RS block length minus R (K = N - R). The RS code implemented uses the primitive polynomial P(x) = x8 + x7 + x2 + x + 1 to generate GF(256). The generator polynomial for the code is:
G(x) =
119 + R i = 120
(x - )
i
An RS block consists of message and redundancy bytes. The number of message bytes in the block, K, is programmable during initialization.
The number of check bytes is R and can be programmed during initialization to be 2 through 20 in increments of 1. The ECC Module may be programmed to output corrections or corrected data. If "corrections" is selected, to obtain corrected data, externally XOR the output correction vector with the corresponding message or check byte. For example, if "corrections" is selected for a block of 200 bytes with errors in locations 100, 123, 153, 176 and 199; output block will be 0's for all locations except for those positions. The bytes output at these positions are referred to as correction vectors and are XOR'd externally with the message bytes to obtain the correct value. If the output of the AHA4013B is programmed to output corrected data, the correction vector is applied internally and the corrected data is output. The Symbol Error Rate Performance of the Reed-Solomon code used is shown in Figure 5.
Figure 5:
Symbol (Byte) Error Rate Performance Curves for Codeword Length = 255 Bytes
10 10 10 10
-0 -2 -4 -6 -8
P
10 10 10 10 10
-10 -12
t=1 t=8 t=5 t=10
-0 -1 -2 -3 -4 -5
-14 -16
t=3
-6 -7 -8
10
10
10
10
P
10
10
10
10
10
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Advanced Hardware Architectures, Inc.
The most common measures of performance for Reed-Solomon code are PUE, PSE, and CBER. PSE is the probability of symbol errors and is the ratio of the number of received symbol errors to the total number of received symbols. In the AHA4013B device the symbol length, m, is equal to 8 bits. PUE is the probability of an uncorrectable error and is the ratio of the number of uncorrectable code blocks to the total number of received code blocks. An uncorrectable error occurs when more than t received symbols are in error. CBER is the Corrected Bit Error Rate. The CBER is the reciprocal of expected number of correct bits between errors. P UE If input noise is random, C BER = -------------- . mxN - 4 with t = 5 , P - 7 and If PSE = 8 x 10 UE = 10 10 - 7 - = 4.9 x 10 -11 . C BER = ----------------8 x 255
This configuration maximizes the ability to correct errors, particularly if R itself has been chosen to be its maximum value of 20. This is the usual choice. This situation causes the CRTN output to flag a message block as uncorrectable at an error level exceeding that of which the device is capable. P < R This increases the level of error detection capability. This situation causes the CRTN output to flag a message block as uncorrectable at an error level below that of which the device is capable. Caveat: Output block may be corrupted if a block exceeds the correction ability of the ECC module.
P=R
The figure shows probability of symbol error and uncorrectable error for block size (N) of 255. It shows the ability of various levels of Reed-Solomon error correction to restore the integrity of the corrupted data. For example, using 255 byte blocks, if 1 out of 1000 of the received bytes have one or more bit errors, RS correction with t = 5 will restore the data to 1 error in 2 million blocks (510 million bytes). For a detailed discussion on error rate performance of Reed-Solomon code, refer to AHA Application Note, Primer: Reed-Solomon Error Correction Codes (ECC), (ANRS01).
2.12 ERASURES
The chip is capable of utilizing erasure information. R erasures may be corrected in any block assuming there are no unmarked errors. The correction capability is: E + 2e R Where E = number of erasures (marked errors) e = number of unmarked errors R = number of check symbols If there are more than P or R erasures the erasure information is discarded, and full error correction is attempted. The chip can be programmed to either call such a block uncorrectable or not. If programmed not to call the block uncorrectable (ERC bit set to 1), the ECC will utilize the full error correction capability to decide if the block is correctable.
2.11
DETERMINING DECODER PERFORMANCE BOUNDARIES
AHA4013B supports a programmable feature that allows a system designer to determine the channel performance. This programmable feature, referred to as error threshold, P, sets a number of errors to be allowed by the chip prior to flagging the block uncorrectable. Erasure Rejection Control bit of the Control Byte register determines the condition of CRTN output pin. P and R are both independently selectable by the user during the Initialization Control Sequence. The various configurations of P and R are described as follows: P > R This is not a sensible choice since this implies that more check bytes are allocated for (correction-only) purposes than there are total check bytes (for both correction and detection). The device will work as if P was set equal to R.
3.0
OPERATIONAL DESCRIPTION
This section describes the relationship of associated signals for various functions of the chip.
3.1
CLOCK
The clock input to the chip must meet the timing requirements shown in Figure 6. The chip is entirely static thus allowing the clock to stop in either the active or inactive state for an indefinite period without loss of stored information.
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PS4013B-0600
Advanced Hardware Architectures, Inc. Figure 6: CLK Characteristics
CLK
1 2 5 3 4
1
NUMBER
1 2 3 4 5
DESCRIPTION
CLK rise time CLK high time CLK fall time CLK low time CLK period
MINIMUM
8
MAXIMUM
5 5
UNITS
nsec nsec nsec nsec nsec
8 20
All timing diagrams in this specification use the clock at the CLK pin as the reference point.
3.2
INITIALIZATION
This section describes the Reset and Initialization Sequence timing. For a detailed discussion on these sequences, refer to Section 2.6 Reset and Initialization Sequence.
Figure 7:
CLK
Initialization and Reset Timing
12
1
2
RSTN DSIN DSO N
3
DI
1
2
3
4
5
6
at le ast 2 clo c k cy cles
Inp ut 6 bytes data for initialization
at le ast 1 cloc k cyc le
at least 2 cloc k cy cles
RESE T
INITIALIZE
D ata
NUMBER
1 2 3
DESCRIPTION
RSTN and DSIN setup time RSTN and DSIN hold time RSTN and DSIN assertion
MINIMUM
7 0 2
MAXIMUM
UNITS
nsec nsec Clock cycles
Initialization bytes are strobed into the device while RSTN and DSIN are low during rising edges of CLK. The RSTN must be active low for at least two clocks before the first initialization byte is strobed in and remain active for at least one clock after the final byte. Initialization register data may be strobed at a minimum of 1 clock per byte. After power-on the initializing registers' contents are undefined. For a detailed description of the Initialization Registers, refer to Section 2.6 Reset and Initialization Sequence.
PS4013B-0600
3.3
DATA INPUT
The chip latches the input data on the DI pins on the rising edge of the CLK when DSIN and RDYIN are both active. The two figures below show the timing diagrams for buffer Ready and buffer Not Ready conditions.
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Advanced Hardware Architectures, Inc. Figure 8: Data Input - Buffer Always Ready
CLK RSTN
DI
12
valid
12
12
12
valid
12
12 valid
12 valid
12 valid
12
12
valid
DSIN
high = erase
ERASE RDYIN
If RSTN is low during write, message bytes are treated as being part of the initialization sequence. If RSTN is high, the data is treated as being part of RS block. In the example above ERASE is asserted high in four sample clocks.
NUMBER
1 2
DESCRIPTION
DI, ERASE and DSIN setup time DI, ERASE and DSIN hold time
MINIMUM
7 0
MAXIMUM
UNITS
nsec nsec
Figure 9:
Data Input - Buffer Not Ready
CLK
RSTN
12 12 12 12
valid
12
valid
12
valid
12
valid
DI DSIN
valid
3
3
3
3
RDYIN
NUMBER
1 2 3
DESCRIPTION
DI, ERASE and DSIN setup time DI, ERASE and DSIN hold time RDYIN output delay
MINIMUM
7 0
MAXIMUM
UNITS
nsec nsec nsec
13
Any input data clocked while RDYIN is inactive are ignored. This is shown in Figure 9.
3.4
DATA OUTPUT
The DO pins are driven from a register clocked on the rising edge of CLK. Valid data on the DO pins is indicated by RDYON being active. When RDYON is inactive, data on the DO pins is undefined, and DSON is ignored. The DSON signal acknowledges receiving the data and is used by the device to internally
Page 14 of 24
increment the address counter and output the next location in the buffer. This data output timing is shown in Figure 10.
PS4013B-0600
Advanced Hardware Architectures, Inc. Figure 10: Data Output
CLK
3 3 valid 12 12 valid 12 12 12 3 valid 12 3 valid 12 12 valid
DO, ERR DSON
4
4
4
RDYON
NUMBER
1 2 3 4
DESCRIPTION
DSON setup time DSON hold time DO output delay RDYON output delay
MINIMUM
8 2 3 3
MAXIMUM
UNITS
nsec nsec nsec nsec
13 13
CRTN is valid for an RS block when the first message byte, XK-1, is strobed out of the chip. Figure 11 shows Reverse Order output. In this operation, CRTN is valid on the last byte of the block from the Output Buffer. In this example only message bytes are output, no check bytes.
Figure 11: CRTN Timing - Reverse Order Output
CLK
3 3
Block m Byte X K-3 Block m Byte X K-2
3
Block m Byte X K-1
3
Block m+1 Byte X 0 Block m+1 Byte X 1
DO DSON
12
12
12
12
12
12
12
12
4
error
CRTN
4
VALID
See Note correctable
4
4
RDYON
Note:
CRTN is active (low) if RS block m is correctable. If the number of errors detected in block m exceeds the error threshold, P, CRTN is inactive (high).
NUMBER
1 2 3 4
DESCRIPTION
DSON setup time DSON hold time DO output delay RDYON, CRTN output delay
MINIMUM
7 2 3 3
MAXIMUM
UNITS
nsec nsec nsec nsec
13 13
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Advanced Hardware Architectures, Inc.
4.0
4.1
SIGNAL SPECIFICATIONS
INPUT SPECIFICATIONS
PIN NUMBER
43 44 1 2 3 4 5 6 42 33 35 41 34
SIGNAL NAME
DI[7] DI[6] DI[5] DI[4] DI[3] DI[2] DI[1] DI[0] DSIN DSON RSTN CLK ERASE
SELF LOAD
(maximum in pF) 10 10 10 10 10 10 10 10 10 10 10 10 10
TSETUP
(min in nsec) 7 7 7 7 7 7 7 7 7 8 7 N/A 7
THOLD
(min in nsec) 0 0 0 0 0 0 0 0 0 2 0 N/A 0
STROBE
CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK N/A CLK
N/A = Not Applicable
(Refer to Section 4.5 DC Electrical Characteristics for pad specifications)
4.2
OUTPUT SPECIFICATIONS
PIN NUMBER
26 24 23 22 21 20 19 18 31 32 28 27
SIGNAL NAME
DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] RDYON RDYIN CRTN ERR
LOAD CAP (maximum in pF)
60 60 60 60 60 60 60 60 60 60 60 60
TDEL (min in nsec)
3 3 3 3 3 3 3 3 3 3 3 3
TDEL (max in nsec)
13 13 13 13 13 13 13 13 13 13 13 13
STROBE REF
CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK
(Refer to Section 4.5 DC Electrical Characteristics for pad specifications)
4.3
POWER & GROUND PINS
PIN NUMBER
8, 10, 11, 16, 17, 29, 30, 37, 40 7, 9, 12, 15, 25, 36, 38, 39
SIGNAL NAME
GND VDD
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Advanced Hardware Architectures, Inc.
4.4
AC ELECTRICAL CHARACTERISTICS
CLOCK RATE Min
0 8 8
Symbol
Fclock Tlow Thigh Trise Tfall
Characteristic
Clock frequency Clock low time Clock high time Clock rise time Clock fall time
Max
50
Units
MHz nsec nsec nsec nsec
Test Conditions
Vil to Vil Vih to Vih Vil to Vih Vil to Vih
5 5
Symbol
Tsetup Thold
Characteristic
Input setup time Input hold time
INPUTS Min
7 0
Max
Units
nsec nsec
Test Conditions
See Notes 1 and 3 See Notes 1 and 2
Notes: 1) Setup and hold times measured from a Vih on the clock input pin. 2) DSON has a 2 nsec hold time. 3) DSON has a 8 nsec setup time.
Symbol
Tout Tout
Note:
Characteristic
DO[7:0] Output delay RDYON, RDYIN, ERR, CRTN Output delay
OUTPUTS Min
3 3
Max
13 13
Units
nsec nsec
Test Conditions
See Note See Note
Output delay measured from Vih on the clock input pin to Vol/Voh on the signal pin. The output loads for the AC test are given in Section 4.2 Output Specifications.
PS4013B-0600
Page 17 of 24
Advanced Hardware Architectures, Inc.
4.5
DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS Characteristic Min Max Units
-55 -0.5 Vss-0.5 150 6.0 Vdd+0.5 deg C V V
Symbol
Test Conditions
Tstg Storage temperature Vdd Supply voltage Vin Input voltage Package: 44-pin PLCC (JEDEC Standard)
Symbol
Vdd Idd Idd Ta P
OPERATING CONDITIONS Characteristic Min Max
Supply voltage Supply current Supply current Operating temperature Power 0 4.75 5.25 1.0 185 70 0.89
Units
V mA mA deg C W
Test Conditions
Static; Clock stopped externally Dynamic
Symbol
Vih Vil Iil Cin
Characteristic
Input high voltage Input low voltage Input leakage Capacitance
INPUTS Min
2.0 Vss -10
Max
Vdd 0.8 10 10
Units
V V pF
Test Conditions
50 MHz 0Symbol
Voh Vol Ioh Iol
Characteristic
Output high voltage Output low voltage Output high current Output low current
OUTPUTS Min
2.4 Vss -8
Max
Vdd 0.4 8
Units
V V mA mA
Test Conditions
Ioh=8mA Iol=8mA Voh=2.4V Vol=0.4V
Page 18 of 24
PS4013B-0600
Advanced Hardware Architectures, Inc.
5.0
PACKAGING
Inches (Millimeters)
PLCC Dimensions B C D E
min .020 (0.51)
A
.050 (1.27)
F
.002 (0.051)
G
.0035 (0.089)
min/max min/max min/max .685/.695 .650/.656 .165/.180 (17.40/17.65) (16.51/16.66) (4.19/4.57)
Packaging
Pin 1 Identification
AHA4013B-050 PJC
CB
YYWWD-(COUNTRY OF ORIGIN) LLLLL
A
D E
F = Lead Planarity
G = Lead Skew
Note: YYWWD = Data Code LLLL = Lead Skew
Complete Package Drawing Available Upon Request.
PS4013B-0600
Page 19 of 24
Advanced Hardware Architectures, Inc.
6.0
6.1
ORDERING INFORMATION
AVAILABLE PARTS
PART NUMBER
AHA4013B-050 PJC
DESCRIPTION
12.5 MBytes/sec Reed-Solomon Error Correction Device
6.2
PART NUMBERING
AHA 4013
Device Number
BRevision Level
050
Speed Designation
P
Package Material
J
C
Manufacturer
Test Package Type Specification
Device Number:
4013B
Package Material Codes:
P Plastic
Package Type Codes:
J J - Leaded Chip Carrier
Test Specifications:
C Commercial 0C to +70C
7.0
RELATED TECHNICAL PUBLICATIONS
PART NUMBER
PB4013B PS4011C PS4012B ABRS03 ABRS04 ABRS06 ABRS09 ABSTD1 ANRS01 ANRS02 ANRS03 ANRS05 RSEVAL IESS-308, Appendix F
DESCRIPTION
AHA Product Brief - AHA4013 12.5 MBytes/sec Reed-Solomon Error Correction Device AHA Product Specification - AHA4011C 10 MBytes/sec Reed-Solomon Error Correction Device AHA Product Specification - AHA4012B 1.5 MBytes/sec Reed-Solomon Error Correction Device AHA Application Brief - AHA4011 and AHA4012 Device Differences AHA Application Brief - Reed-Solomon Evaluation Software Version 3.0 AHA Application Brief - AHA4011 and AHA4013 Device Differences AHA Application Brief - AHA4013A and AHA4013B Device Differences AHA Application Brief - AHA Data Compression and Forward Error Correction Standards AHA Application Note - Primer: Reed-Solomon Error Correction Codes (ECC) AHA Application Note - Interleaving for Burst Error Correction AHA Application Note - Reed-Solomon Evaluation Software Version 3.0 AHA Application Note - Serial I/O Interface to AHA4011/AHA4012 Reed-Solomon Evaluation Software Version 3.0 (Windows) Concatenation of Reed-Solomon (RS) Outer Coding with the Existing Inner FEC (Not available from AHA)
Page 20 of 24
PS4013B-0600
Advanced Hardware Architectures, Inc.
APPENDIX A
Table of Elements BLOCK SIZE `N'
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93 97 101 105 109 113 117 121 125 129 133 137 141 145 149 153 157 161 165 169 173 177 181 185
PS4013B-0600
HEX VALUE
1 10 87 dd 6f ec 71 8b 1d 57 62 3c ce d8 3f fe d6 df 4f 65 4c 55 42 b5 f3 6 60 1c 47 e5 e1 a1 34 4e 75 cb 88 2d 59 82 8d 7d 4b 25 d9 2f 79
BLOCK SIZE `N'
2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186
HEX VALUE
2 20 89 3d de 5f e2 91 3a ae c4 78 1b 37 7e 7b 2b 39 9e ca 98 aa 84 ed 61 c c0 38 8e 4d 45 c5 68 9c ea 11 97 5a b2 83 9d fa 96 4a 35 5e f2
BLOCK SIZE `N'
3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 71 75 79 83 87 91 95 99 103 107 111 115 119 123 127 131 135 139 143 147 151 155 159 163 167 171 175 179 183 187
HEX VALUE
4 40 95 7a 3b be 43 a5 74 db f f0 36 6e fc f6 56 72 bb 13 b7 d3 8f 5d c2 18 7 70 9b 9a 8a d d0 bf 53 22 a9 b4 e3 81 bd 73 ab 94 6a bc 63
BLOCK SIZE `N'
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188
HEX VALUE
8 80 ad f4 76 fb 86 cd e8 31 1e 67 6c dc 7f 6b ac e4 f1 26 e9 21 99 ba 3 30 e e0 b1 b3 93 1a 27 f9 a6 44 d5 ef 41 85 fd e6 d1 af d4 ff c6
Page 21 of 24
Advanced Hardware Architectures, Inc. BLOCK SIZE `N'
189 193 197 201 205 209 213 217 221 225 229 233 237 241 245 249 253
HEX VALUE
b b0 a3 14 c7 48 15 d7 cf c8 b8 23 b9 33 3e ee 51
BLOCK SIZE `N'
190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254
HEX VALUE
16 e7 c1 28 9 90 2a 29 19 17 f7 46 f5 66 7c 5b a2
BLOCK SIZE `N'
191 195 199 203 207 211 215 219 223 227 231 235 239 243 247 251 255
HEX VALUE
2c 49 5 50 12 a7 54 52 32 2e 69 8c 6d cc f8 b6 c3
BLOCK SIZE `N'
192 196 200 204 208 212 216 220 224 228 232 236 240 244 248 252
HEX VALUE
58 92 a a0 24 c9 a8 a4 64 5c d2 9f da 1f 77 eb
For example, for a block size of 205, the value to be programed in Byte 1 of the Initialization Register is 0xc7. /*This is a C program to generate Table of Elements. Pass a value of block length, N in decimal to this, and obtain the Element value in hex.*/ int alpha(n) int n; { int i,b,c; c=01; for (i=1;i0377) b=b^0607; c=b; } return c; } main() { int i; printf("Enter N--> "); scanf("%d",&i); if(i<1 || i>255) printf("1<=N<=255"); else printf("\nN = %d\tALPHA = %2x\n\n", i, alpha(i)); }
Page 22 of 24
PS4013B-0600
Advanced Hardware Architectures, Inc.
APPENDIX B
AHA4013B Data Rate Calculations in Continuous Operation
Assumptions and Equations: 1) 50 MHz Clock is used. 2) Input Rate (Ci) = Output Rate (Co)
i 3) Latency = Ci x ( N - 1 ) + ( R + 60 ) + N x --------------
C Ci - 1
4) Data Rate = 50 MHz/Ci clocks/byte 5) GOOD or BAD based on inequality equation:
Cm R + 60 + N x --------------Cm - 1 ------------------------------------------------ + N 367 Ci
(5)
6) GOOD or BAD based on inequality equation:
Ci Cm ( N - 1 ) x C i R + 48 + N x ------------- + N x --------------Ci - 1 Cm - 1
(6)
7) Check symbols are input into and output from the chip along with message symbols.
Note: The following tables show examples of Data Rates and Latencies for various block sizes. Other block sizes are also possible.
CLOCKS N /BYTE
4 4 4 4 4 4 4 4 4 4 4 4 4 25 50 53 75 100 126 194 208 219 200 225 250 255
T
10 10 10 10 10 7 8 8 9 10 10 10 10
MAXIMUM LATENCY DATA RATE EQUATION 5 EQUATION 6 CLOCKS SECONDS (MB/sec)
209 343 359 476 609 742 1107 1181 1242 1143 1276 1409 1436 4.18 6.86 7.18 9.52 12.16 14.88 22.16 23.60 24.88 22.88 25.52 28.16 28.72 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD BAD BAD BAD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD
CLOCKS N /BYTE
4 4 4 4 4 4 4 4 4 4 4
PS4013B-0600
T
5 5 5 5 5 5 5 5 5 5 5
MAXIMUM LATENCY DATA RATE EQUATION 5 EQUATION 6 CLOCKS SECONDS (MB/sec)
199 333 466 599 733 866 999 1133 1266 1399 1426 3.98 6.66 9.36 12.00 14.64 17.36 20.00 22.64 25.36 28.00 28.56 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD BAD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD
Page 23 of 24
25 50 75 100 125 150 175 200 225 250 255
Advanced Hardware Architectures, Inc.
CLOCKS N /BYTE
4 4 4 4 4 4 4 4 4 4 4 25 50 75 100 125 150 175 200 225 250 255
T
3 3 3 3 3 3 3 3 3 3 3
MAXIMUM LATENCY DATA RATE EQUATION 5 EQUATION 6 CLOCKS SECONDS (MB/sec)
195 329 462 595 729 862 995 1129 1262 1395 1422 3.90 6.58 9.28 11.92 14.56 17.28 19.92 22.56 25.28 27.92 28.48 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD BAD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD
CLOCKS N /BYTE
4 4 4 4 4 4 4 4 4 4 4 25 50 75 100 125 150 175 200 225 250 255
T
1 1 1 1 1 1 1 1 1 1 1
MAXIMUM LATENCY DATA RATE EQUATION 5 EQUATION 6 CLOCKS SECONDS (MB/sec)
191 325 458 591 725 858 991 1125 1258 1391 1418 3.82 6.50 9.20 11.84 14.48 17.20 19.84 22.48 25.20 27.84 28.40 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 12.50 GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD BAD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD GOOD
Page 24 of 24
PS4013B-0600

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